The invention relates to a circuit arrangement for generating a defined output signal in a CMOS circuit, comprising a sensor signal conditioning switch with an output to emit an output signal, where the output is connected to a first connection of a load resistor and the second connection of the load resistor is connected to a VDD potential.
In addition, the invention relates to a circuit arrangement for generating a defined output signal in a CMOS circuit comprising a sensor signal conditioning switch with an output to emit an output signal, where the output is connected to a first connection of a load resistor and the second connection of the load resistor is connected to a VSS potential.
Circuits for conditioning sensor signals are designed to transform the more or less error-prone raw signals of sensors into a standard output signal which is free of said errors. One of the frequently used standards is the ratiometric voltage output. It is used to transform the relevant range of the input signal, for example an angle sensor angle of 50 to 150 degrees or the pressure sensor pressure of 0 to 200 bar into an output voltage of for example 5% to 95% of the supply voltage.
The standard of the ratiometric voltage signal originates from simple potentiometric sensors. Compatibility requirements make it necessary that modern CMOS circuits behave exactly like their predecessors, the potentiometers, with respect to certain errors.
In particular, it is necessary that in the so-called “power loss” case, i.e. when one of the VDD and GND supply lines is interrupted, an output signal is generated in cooperation with the remaining connected load resistor in one of the so-called diagnostic ranges, namely below 2.5% or above 97.5% of the supply voltage.
When using a CMOS circuit without any external components, a special circuit design is required to comply with this behavior which occurs naturally in a potentiometer.
The solution corresponding to the state-of-the art consists in the detection of the interruption of the supply voltage and to bring the circuit into a high-resistance status which makes is possible to generate an output voltage smaller than 2.5% of VDD in combination with a pull-down load resistor in case of “loss of VSS” or a supply voltage greater than 97.5% with a pull-up load resistor in case of “loss of VDD”.
The issues described below must be taken into account for this purpose.
In order to achieve the diagnostic status, the diagnosis switch as component of the circuit must continue to perform certain functions while the supply voltage connections are interrupted. Before the supply voltage drops below a certain value due to the voltage requirements of the circuit, the whole circuit must have been switched into power-down status to ensure the supply of the circuit via load resistor and parasitic substrate or tank diodes. Mastering this switching process under different framework conditions such as load resistor size and load capacity and essentially undefined flank development of the interruption is a technical challenge.
The realization of the power-down status with extremely low residual voltage for the whole circuit requires special technical procedures in each individual switching block which in part can only be achieved at the expense of the overall error budget of critical analogous switching parts. In addition, the linkage of the diagnosis switch with all switching parts represents an additional design risk for the proper functioning of all other control procedures which should not be underestimated.
Under real conditions, in particular when used in an automobile, the secure maintenance of the residual power-down voltage below a value which ensures compliance with the diagnosis levels (<2.5% VDD or >97% VDD) even for temperatures of 150° C. and more, is problematic. To manage this problem, a maximum limit needs to be specified for the load resistor which is generally uncommon; in the practice, this limits the application range of the circuit.